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参数资料
| 型号： | EP20K400BI652-1 |
| 元件分类： | 电源监测 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 双电压监视器集成CPU监控 |
| 文件页数： | 28/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K400BI652-1 |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
The counter mode uses two three-input LUTs: one generates the counter
data, and the other generates the fast carry bit. A 2-to-1 multiplexer
provides synchronous loading, and another AND gate provides
synchronous clearing. If the cascade function is used by an LE in counter
mode, the synchronous clear or load overrides any signal carried on the
cascade chain. The synchronous clear overrides the synchronous load.
LEs in arithmetic mode can drive out registered and unregistered versions
of the LUT output.
Clear & Preset Logic Control
Logic for the register’s clear and preset signals is controlled by LAB-wide
signals. The LE directly supports an asynchronous clear function. The
Quartus II software Compiler can use a NOT-gate push-back technique to
emulate an asynchronous preset. Moreover, the Quartus II software
Compiler can use a programmable NOT-gate push-back technique to
emulate simultaneous preset and clear or asynchronous load. However,
this technique uses three additional LEs per register. All emulation is
performed automatically when the design is compiled. Registers that
emulate simultaneous preset and load will enter an unknown state upon
power-up or when the chip-wide reset is asserted.
In addition to the two clear and preset modes, APEX 20K devices provide
a chip-wide reset pin (DEV_CLRn) that resets all registers in the device.
Use of this pin is controlled through an option in the Quartus II software
that is set before compilation. The chip-wide reset overrides all other
control signals. Registers using an asynchronous preset are preset when
the chip-wide reset is asserted; this effect results from the inversion
technique used to implement the asynchronous preset.
FastTrack Interconnect
In the APEX 20K architecture, connections between LEs, ESBs, and I/O
pins are provided by the FastTrack Interconnect. The FastTrack
Interconnect is a series of continuous horizontal and vertical routing
channels that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect consists of row and column interconnect
channels that span the entire device. The row interconnect routes signals
throughout a row of MegaLAB structures; the column interconnect routes
signals throughout a column of MegaLAB structures. When using the row
and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,
or ESB in a device. See Figure 9.
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K400BI652-1ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400BI652-2ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400BI652-3 | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400BI652-3ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400CB652I7ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K400BI652-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K400BI652-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K400BI652-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K400BI652-2V | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K400BI652-3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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