- 您现在的位置：买卖IC网 > PDF目录97919 > EP20K400CB652I8ES Dual Voltage Monitor with Intergrated CPU Supervisor PDF资料下载
参数资料
| 型号： | EP20K400CB652I8ES |
| 元件分类： | 电源监测 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 双电压监视器集成CPU监控 |
| 文件页数： | 2/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K400CB652I8ES |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页
10
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20K devices provide two dedicated clock pins and four dedicated
input pins that drive register control inputs. These signals ensure efficient
distribution of high-speed, low-skew control signals. These signals use
dedicated routing channels to provide short delays and low skews. Four
of the dedicated inputs drive four global signals. These four global signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally generated asynchronous clear signals with high
fan-out. The dedicated clock pins featured on the APEX 20K devices can
also feed logic. The devices also feature ClockLock and ClockBoost clock
management circuitry. APEX 20KE devices provide two additional
dedicated clock pins, for a total of four dedicated clock pins.
MegaLAB Structure
APEX 20K devices are constructed from a series of MegaLABTM
structures. Each MegaLAB structure contains a group of logic array blocks
(LABs), one ESB, and a MegaLAB interconnect, which routes signals
within the MegaLAB structure. The EP20K30E device has 10 LABs,
EP20K60E through EP20K600E devices have 16 LABs, and the
EP20K1000E and EP20K1500E devices have 24 LABs. Signals are routed
between MegaLAB structures and I/O pins via the FastTrack
Interconnect. In addition, edge LABs can be driven by I/O pins through
the local interconnect. Figure 2 shows the MegaLAB structure.
Figure 2. MegaLAB Structure
ESB
MegaLAB Interconnect
Local
Interconnect
To Adjacent
LAB or IOEs
LABs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K400CB652I9ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400CF672I7ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400CF672I8ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400CF672I9ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
| EP20K400EBC652-1ES | Dual Voltage Monitor with Intergrated CPU Supervisor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K400CB652I9ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EP20K400CF672C7 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K400CF672C7GA | 制造商:Altera Corporation 功能描述: |
| EP20K400CF672C8 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K400CF672C8N | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。