参数资料
型号: EP20K400FI672-1
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 现场可编程门阵列(FPGA)
文件页数: 41/114页
文件大小: 1623K
代理商: EP20K400FI672-1
32
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Read/Write Clock Mode
The read/write clock mode contains two clocks. One clock controls all
registers associated with writing: data input, WE, and write address. The
other clock controls all registers associated with reading: read enable
(RE), read address, and data output. The ESB also supports clock enable
and asynchronous clear signals; these signals also control the read and
write registers independently. Read/write clock mode is commonly used
for applications where reads and writes occur at different system
frequencies. Figure 20 shows the ESB in read/write clock mode.
Figure 20. ESB in Read/Write Clock Mode
Notes:
(1)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2)
APEX 20KE devices have four dedicated clocks.
Dedicated Clocks
2 or 4
4
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
128
× 16
256
× 8
512
× 4
1,024
× 2
2,048
× 1
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
outclken
inclken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Dedicated Inputs &
Global Signals
to MegaLAB,
FastTrack &
Local
Interconnect
(2)
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相关代理商/技术参数
参数描述
EP20K400FI672-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400FI672-2 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
EP20K400FI672-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400FI672-2V 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K400FI672-3 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)