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参数资料
型号： EP20K600E
厂商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可编程逻辑器件系列
文件页数： 62/117页
文件大小： 570K
代理商： EP20K600E
62
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to
Tables 23
through
26
:
(1)
See the
Operating Requirements for Altera Devices Data Sheet
.
(2)
All APEX 20K devices are 5.0-V tolerant.
(3)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(4)
Numbers in parentheses are for industrial-temperature-range devices.
(5)
Maximum V
CC
rise time is 100 ms, and V
CC
must rise monotonically.
(6)
All pins, including dedicated inputs, clock I/O, and JTAG pins, may be driven before V
CCINT
and V
CCIO
are
powered.
(7)
Typical values are for T
A
= 25
° C,
V
= 2.5 V, and V
= 2.5 or 3.3 V.
(8)
These values are specified in the APEX 20K device recommended operating conditions, shown in Table 26 on
page 62.
(9)
The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when V
CCIO
and
V
CCINT
meet the relationship shown in Figure 33 on page 68.
(10) The I
OH
parameter refers to high-level TTL, PCI or CMOS output current.
(11) The I
OL
parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(12) This value is specified for normal device operation. The value may vary during power-up.
(13) Pin pull-up resistance values will be lower if an external source drives the pin higher than V
CCIO
.
(14) Capacitance is sample-tested only.
Tables 27
through
30
provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 1.8-V APEX 20KE devices.
Table 26. APEX 20K 5.0-V Tolerant Device Capacitance
Notes (2)
,
(14)
Symbol
Parameter
Conditions
Min
Max
Unit
C
IN
C
INCLK
Input capacitance
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
8
pF
Input capacitance on dedicated
clock pin
12
pF
C
OUT
Output capacitance
V
OUT
= 0 V, f = 1.0 MHz
8
pF
Table 27. APEX 20KE Device Absolute Maximum Ratings
Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
V
CCINT
V
CCIO
V
I
I
OUT
T
STG
T
AMB
T
J
Supply voltage
With respect to ground
(2)
–0.5
2.5
V
–0.5
4.6
V
DC input voltage
–0.5
4.6
V
DC output current, per pin
–25
25
mA
Storage temperature
No bias
–65
150
° C
Ambient temperature
Under bias
–65
135
° C
Junction temperature
PQFP, RQFP, TQFP, and BGA packages,
under bias
135
° C
Ceramic PGA packages, under bias
150
° C
相关PDF资料
PDF描述
EP20K60E Programmable Logic Device Family
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EP20K600EBC652-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K600EBC652-1X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2432 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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EP20K600EBC652-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
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