参数资料
型号: EP20K60ERC240
厂商: ALTERA CORP
元件分类: PLD
英文描述: LOADABLE PLD, PQFP240
封装: 34.90 X 34.90 MM, 0.50 MM PITCH, RQFP-240
文件页数: 13/114页
文件大小: 4116K
代理商: EP20K60ERC240
Altera Corporation
11
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus Compiler places associated logic within an LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
Figure 3. LAB Structure
To/From
Adjacent LAB,
ESB, or IOEs
To/From
Adjacent LAB,
ESB, or IOEs
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Local Interconnect
LEs drive local
MegaLAB, row,
and column
interconnects.
Column
Interconnect
Row
Interconnect
MegaLAB Interconnect
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EP20K60ETC144 LOADABLE PLD, PQFP144
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相关代理商/技术参数
参数描述
EP20K60ERC240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K60ERC240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K60ERC240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K60ERI208-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K60ERI208-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA