参数资料
型号: EP224LC-7A
厂商: Altera Corporation
英文描述: Classic EPLDs
中文描述: 经典EPLDs
文件页数: 13/16页
文件大小: 265K
代理商: EP224LC-7A
Altera Corporation
13
EP220 & EP224 Classic EPLDs
AC Operating Conditions: -7A, -10A, & -12 Speed Grades
Note (1)
Notes to tables:
(1)
Operating conditions: V
CC
= 5 V
±
5
%
, T
A
= 0
°
C to 70
°
C for commercial use.
V
CC
= 5 V
±
5
%
, T
A
= –40
°
C to 85
°
C for industrial use.
(2)
If the device enters standby mode and remains inactive for approximately 75 ns, increase the time by the amount
shown. For EP220-10A, EP220-12, and EP224-10A, EP224-12 devices only.
(3)
Measured with all outputs switching.
(4)
The
t
PZX
and
t
PXZ
parameters are measured at
±
0.5 V from steady-state voltage that is driven by the specified
output load. The
t
PXZ
parameter is measured with C
L
= 5 pF and with all eight outputs switching.
Combinatorial Mode
EP220-7A
EP224-7A
EP220-10A
EP224-10A
EP220-12
EP224-12
Non-Turbo
Adder
Symbol
Parameter
Min Max Min Max Min Max
Note (2)
Units
t
PD1
t
PD2
t
PZX
t
PXZ
t
OSR
t
OSC
Input to non-registered output,
Note (3)
7.5
10
12
20
ns
I/O to non-registered output,
Note (3)
7.5
10
12
20
ns
Input or I/O to output enable,
Note (4)
9
12
12
20
ns
Input or I/O to output disable,
Note (4)
9
10
12
20
ns
Register-mode output to output skew
300
-
-
-
ps
Combinatorial-mode output to output skew
400
-
-
-
ps
Synchronous Clock Mode
EP220-7A
EP224-7A
EP220-10A
EP224-10A
EP220-12
EP224-12
Non-Turbo
Adder
Symbol
Parameter
Min Max Min Max Min Max
Note (2)
Units
f
MAX
Maximum frequency (pipelined), no feedback,
Note (3)
115
111
90.9
-
MHz
f
CNT1
Maximum counter frequency, external feedback,
Note (3)
100
80
66
-
MHz
f
CNT2
Maximum counter frequency, internal feedback,
Note (3)
115
100
83.3
-
MHz
t
SU1
t
H
t
CO1
t
CO2
Input or I/O setup time to global clock
4.5
7
9
20
ns
Input or I/O hold time from global clock
0
0
0
0
ns
Global clock to output delay, Note
(3)
5.5
5.5
6
0
ns
Global clock to output delay through combinatorial
macrocell
10
13
15
20
ns
t
CNT
t
CL
t
CH
t
CP
Minimum global clock period,
Note (3)
10
10
12
20
ns
Clock low time
4
4
5
0
ns
Clock high time
4
4
5
0
ns
Clock period
10
9
11
0
ns
相关PDF资料
PDF描述
EP224PC-10 Classic EPLDs
EP224PC-10A Classic EPLDs
EP224PC-12 Classic EPLDs
EP224PC-7 Classic EPLDs
EP2C20 SECTION IV. I/O STANDARDS
相关代理商/技术参数
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