参数资料
型号: EP2AGX45DF25C5N
厂商: Altera
文件页数: 64/90页
文件大小: 0K
描述: IC ARRIA II GX FPGA 45K 572FBGA
产品培训模块: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
标准包装: 5
系列: Arria II GX
LAB/CLB数: 1805
逻辑元件/单元数: 42959
RAM 位总计: 3517440
输入/输出数: 252
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 572-FBGA
供应商设备封装: 572-FBGA
其它名称: 544-2643
Chapter 1: Device Datasheet for Arria II Devices
1–59
Switching Characteristics
December 2013
Altera Corporation
Table 1–49 lists the embedded memory block specifications for Arria II GZ devices.
Table 1–49. Embedded Memory Block Performance Specifications for Arria II GZ Devices (Note 1)
Memory
Mode
Resources Used
Performance
Unit
ALUTs
TriMatrix
Memory
C3
I3
C4
I4
MLAB
Single port 64 × 10
0
1
500
450
MHz
Simple dual-port 32 × 20
0
1
500
450
MHz
Simple dual-port 64 × 10
0
1
500
450
MHz
ROM 64 × 10
0
1
500
450
MHz
ROM 32 × 20
0
1
500
450
MHz
M9K
Block (2)
Single-port 256 × 36
0
1
540
475
MHz
Simple dual-port 256 × 36
0
1
490
420
MHz
Simple dual-port 256 × 36, with the
read-during-write option set to Old
Data
0
1
340
300
MHz
True dual port 512 × 18
0
1
430
370
MHz
True dual-port 512 × 18, with the
read-during-write option set to Old
Data
0
1
335
290
MHz
ROM 1 Port
0
1
540
475
MHz
ROM 2 Port
0
1
540
475
MHz
Min Pulse Width (clock high time)
800
850
ps
Min Pulse Width (clock low time)
625
690
ps
M144K
Block (2)
Single-port 2K × 72
0
1
440
400
380
350
MHz
Simple dual-port 2K × 72
0
1
435
375
385
325
MHz
Simple dual-port 2K × 72, with the
read-during-write option set to Old
Data
0
1
240
225
205
200
MHz
Simple dual-port 2K × 64 (with ECC)
0
1
300
295
255
250
MHz
True dual-port 4K × 36
0
1
375
350
330
310
MHz
True dual-port 4K × 36, with the
read-during-write option set to Old
Data
0
1
230
225
205
200
MHz
ROM 1 Port
0
1
500
450
435
420
MHz
ROM 2 Port
0
1
465
425
400
MHz
Min Pulse Width (clock high time)
755
860
950
ps
Min Pulse Width (clock low time)
625
690
ps
Notes to Table 1–48:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection CRC feature, there is no degradation in FMAX.
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