参数资料
型号: EP2AGX95EF35C4N
厂商: Altera
文件页数: 21/90页
文件大小: 0K
描述: IC ARRIA II GX FPGA 95K 1152FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 3
系列: Arria II GX
LAB/CLB数: 3747
逻辑元件/单元数: 89178
RAM 位总计: 6839296
输入/输出数: 452
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 1152-BBGA
供应商设备封装: 1152-FBGA(27x27)
1–20
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
December 2013
Altera Corporation
Table 1–33 lists the differential I/O standard specifications for Arria II GZ devices.
Power Consumption for the Arria II Device Family
Altera offers two ways to estimate power for a design:
Using the Microsoft Excel-based Early Power Estimator
Using the Quartus II PowerPlay Power Analyzer feature
The interactive Microsoft Excel-based Early Power Estimator is typically used prior to
designing the FPGA in order to get a magnitude estimate of the device power. The
Quartus II PowerPlay Power Analyzer provides better quality estimates based on the
specifics of the design after place-and-route is complete. The PowerPlay Power
Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities which, when combined with detailed circuit models, can yield very
accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the
Quartus II Handbook.
Table 1–33. Differential I/O Standard Specifications for Arria II GZ Devices (Note 1)
I/O
Standard
VCCIO (V)
VID (mV)
VICM(DC) (V)
VOD (V) (3)
VOCM (V) (3)
Min
Typ
Max
Min
Cond.
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
2.5 V
LVDS
(HIO)
2.375
2.5
2.625
100
VCM =
1.25 V
0.05
1.8
0.247
0.6
1.125
1.25
1.375
2.5 V
LVDS
(VIO)
2.375
2.5
2.625
100
VCM =
1.25 V
0.05
1.8
0.247
0.6
1
1.25
1.5
RSDS
(HIO)
2.375
2.5
2.625
100
VCM =
1.25 V
0.3
1.4
0.1
0.2
0.6
0.5
1.2
1.4
RSDS
(VIO)
2.375
2.5
2.625
100
VCM =
1.25 V
0.3
1.4
0.1
0.2
0.6
0.5
1.2
1.5
Mini-LVDS
(HIO)
2.375
2.5
2.625
200
600
0.4
1.32
5
0.25
0.6
1
1.2
1.4
Mini-LVDS
(VIO)
2.375
2.5
2.625
200
600
0.4
1.32
5
0.25
0.6
1
1.2
1.5
LVPECL
2.375
2.5
2.625
300
0.6
1.8
2.375
2.5
2.625
100
Notes to Table 1–33:
(1) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–21.
(2) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(3) RL range: 90 RL 110 .
(4) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. These specifications depend on the system topology.
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EP2AGX95EF35C5NES 制造商:Altera Corporation 功能描述:IC ARRIA II GX FPGA 1152FBGA
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