参数资料
型号: EP4CE115F29I8LN
厂商: Altera
文件页数: 22/42页
文件大小: 0K
描述: IC CYCLONE IV FPGA 115K 780-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色产品: Cyclone? IV FPGAs
标准包装: 36
系列: CYCLONE® IV E
LAB/CLB数: 7155
逻辑元件/单元数: 114480
RAM 位总计: 3981312
输入/输出数: 528
电源电压: 0.97 V ~ 1.03 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 780-BBGA
供应商设备封装: 780-FBGA(29x29)
Chapter 1: Cyclone IV Device Datasheet
1–29
Switching Characteristics
December 2013
Altera Corporation
tLOCK (3)
1
—1—
1
—1—
1
ms
Notes to Table 1–31:
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) Cyclone IV E devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the
output pin of all I/O Banks.
Cyclone IV GX devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated RSDS transmitter is supported at the output
pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(3) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7
speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 1 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK (input
clock
frequency)
×10
5
85
5
85
5
85
5
85
5
72.5
MHz
×8
5
85
5
85
5
85
5
85
5
72.5
MHz
×7
5
85
5
85
5
85
5
85
5
72.5
MHz
×4
5
85
5
85
5
85
5
85
5
72.5
MHz
×2
5
85
5
85
5
85
5
85
5
72.5
MHz
×1
5
170
5
170
5
170
5
170
5
145
MHz
Device
operation in
Mbps
×10
100
170
100
170
100
170
100
170
100
145
Mbps
×8
80
170
80
170
80
170
80
170
80
145
Mbps
×7
70
170
70
170
70
170
70
170
70
145
Mbps
×4
40
170
40
170
40
170
40
170
40
145
Mbps
×2
20
170
20
170
20
170
20
170
20
145
Mbps
×1
10
170
10
170
10
170
10
170
10
145
Mbps
tDUTY
45
55
45
55
45
55
45
55
45
55
%
TCCS
200
200
200
200
200
ps
Output jitter
(peak to peak)
500
500
550
600
700
ps
tRISE
20 – 80%,
CLOAD =
5pF
500
500
500
500
500
ps
tFALL
20 – 80%,
CLOAD =
5pF
500
500
500
500
500
ps
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