参数资料
| 型号： | EP4CE55F29I7 |
| 厂商： | Altera |
| 文件页数： | 3/42页 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV FPGA 55K 780FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? IV FPGAs |
| 标准包装： | 36 |
| 系列： | CYCLONE® IV E |
| LAB/CLB数： | 3491 |
| 逻辑元件/单元数： | 55856 |
| RAM 位总计： | 2396160 |
| 输入/输出数： | 374 |
| 电源电压： | 1.15 V ~ 1.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 780-BBGA |
| 供应商设备封装： | 780-FBGA（29x29） |
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Chapter 1: Cyclone IV Device Datasheet
1–11
Operating Conditions
December 2013
Altera Corporation
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 1–12 lists the weak pull-up and pull-down resistor values for Cyclone IV
devices.
Hot-Socketing
Table 1–13 lists the hot-socketing specifications for Cyclone IV devices.
1 During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin
capacitance is less than 20 pF.
Table 1–12. Internal Weak Pull
-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R_PU
Value of the I/O pin pull-up resistor
before and during configuration, as
well as user mode if you enable the
programmable pull-up resistor option
725
41
k
728
47
k
835
61
k
10
57
108
k
13
82
163
k
19
143
351
k
R_PD
Value of the I/O pin pull-down resistor
before and during configuration
619
30
k
622
36
k
625
43
k
735
71
k
8
50
112
k
Notes to Table 1–12:
(1) All I/O pins have an option to enable weak pull
-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG TCK.
(2) Pin pull
-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) R_PU = (VCCIO –VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC –5%;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Table 1–13. Hot
-Socketing Specifications for Cyclone IV Devices
Symbol
Parameter
Maximum
IIOPIN(DC)
DC current per I/O pin
300
A
IIOPIN(AC)
AC current per I/O pin
8 mA (1)
IXCVRTX(DC)
DC current per transceiver TX pin
100 mA
IXCVRRX(DC)
DC current per transceiver RX pin
50 mA
Note to Table 1–13:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4CE55F29I7N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 3491 LABs 374 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE55F29I8L | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 3491 LABs 374 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE55F29I8LN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 3491 LABs 374 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE55U19I7N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE6 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:引脚资料 |
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