参数资料
型号: EP4CE6F17I8L
厂商: Altera
文件页数: 11/42页
文件大小: 0K
描述: IC CYCLONE IV FPGA 6K 256FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色产品: Cyclone? IV FPGAs
标准包装: 90
系列: CYCLONE® IV E
LAB/CLB数: 392
逻辑元件/单元数: 6272
RAM 位总计: 276480
输入/输出数: 179
电源电压: 0.97 V ~ 1.03 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 256-BGA
供应商设备封装: 256-FBGA(17x17)
Chapter 1: Cyclone IV Device Datasheet
1–19
Switching Characteristics
December 2013
Altera Corporation
Signal detect/loss
threshold
PIPE mode
65
175
65
175
65
175
mV
tLTR (10)
75
75——
75
s
tLTR-LTD_Manual (11)
15—
15
—15—
s
tLTD (12)
0
100
4000
0
100
4000
0
100
4000
ns
tLTD_Manual (13)
4000
4000
4000
ns
tLTD_Auto (14)
4000
4000
4000
ns
Receiver buffer and
CDR offset
cancellation time
(per channel)
17000
17000
17000
recon
fig_c
lk
cycles
Programmable DC
gain
DC Gain Setting =
0
—0
0
0
dB
DC Gain Setting =
1
—3
3
3
dB
DC Gain Setting =
2
—6
6
6
dB
Transmitter
Supported I/O
Standards
1.5 V PCML
Data rate (F324 and
smaller package)
600
2500
600
2500
600
2500
Mbps
Data rate (F484 and
larger package)
600
3125
600
3125
600
2500
Mbps
VOCM
0.65 V setting
650
650
650
mV
Differential on-chip
termination resistors
100
setting
100
100
100
150
setting
150
150
150
Differential and
common mode
return loss
PIPE, CPRI LV,
Serial Rapid I/O
SR, SDI, XAUI,
SATA
Compliant
Rise time
50
200
50
200
50
200
ps
Fall time
50
200
50
200
50
200
ps
Intra-differential pair
skew
15
15
15
ps
Intra-transceiver
block skew
120
120
120
ps
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 3 of 4)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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