参数资料
| 型号： | EP4CGX110DF31I7N |
| 厂商： | Altera |
| 文件页数： | 20/42页 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV FPGA 110K 896FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? IV FPGAs |
| 标准包装： | 27 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB数： | 6839 |
| 逻辑元件/单元数： | 109424 |
| RAM 位总计： | 5621760 |
| 输入/输出数： | 475 |
| 电源电压： | 1.16 V ~ 1.24 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 896-BBGA |
| 供应商设备封装： | 896-FBGA（31x31） |
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Chapter 1: Cyclone IV Device Datasheet
1–27
Switching Characteristics
December 2013
Altera Corporation
Table 1–29 lists the active configuration mode specifications for Cyclone IV devices.
Table 1–30 lists the JTAG timing parameters and values for Cyclone IV devices.
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
Table 1–29. Active Configuration Mode Specifications for Cyclone IV Devices
Programming Mode
DCLK Range
Typical DCLK
Unit
Active Parallel (AP) (1)
20 to 40
33
MHz
Active Serial (AS)
20 to 40
33
MHz
Note to Table 1–29:
(1) AP configuration mode is only supported for Cyclone IV E devices.
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices (1)
Symbol
Parameter
Min
Max
Unit
tJCP
TCK clock period
40
—
ns
tJCH
TCK clock high time
19
—
ns
tJCL
TCK clock low time
19
—
ns
tJPSU_TDI
JTAG port setup time for TDI
1
—
ns
tJPSU_TMS JTAG port setup time for TMS
3
—
ns
tJPH
JTAG port hold time
10
—
ns
tJPCO
—15
ns
tJPZX
JTAG port high impedance to valid output (2), (3)
—15
ns
tJPXZ
JTAG port valid output to high impedance (2), (3)
—15
ns
tJSSU
Capture register setup time
5
—
ns
tJSH
Capture register hold time
10
—
ns
tJSCO
Update register clock to output
—
25
ns
tJSZX
Update register high impedance to valid output
—
25
ns
tJSXZ
Update register valid output to high impedance
—
25
ns
Notes to Table 1–30:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–37.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4CGX110F17C8 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX110F23C8N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX110F23I7N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX15 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
| EP4CGX150 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
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