参数资料
| 型号： | EP4SE820H35C3 |
| 厂商： | Altera |
| 文件页数： | 77/82页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 820K 1152HBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | STRATIX® IV E |
| LAB/CLB数： | 32522 |
| 逻辑元件/单元数： | 813050 |
| RAM 位总计： | 34093056 |
| 输入/输出数： | 744 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1152-BBGA 裸露焊盘 |
| 供应商设备封装： | 1152-HBGA（40x40） |
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SIV54002-1.5
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
February 2011
2. Addendum to the Stratix IV Device
Handbook
This chapter describes changes to the published version of the Stratix IV Device
Handbook. All changes from Revision 1.4 of this chapter are now incorporated in the
main handbook chapters or in AN 612: Decision Feedback Equalization in Stratix IV
Adaptive Equalization (AEQ)
f This AEQ information is now located in the Dynamic Reconfiguration in Stratix IV
Devices chapter.
Decision Feedback Equalization (DFE)
f For more information about the DFE feature, refer to AN 612: Decision Feedback
Power-On Reset Circuitry
The Power-On Reset Circuitry information is now located in the Hot Socketing and
Power-On Reset in Stratix IV Devices chapter.
Power-On Reset Specifications
f The Power-On Reset Specification information is now located in the Hot Socketing and
Power-On Reset in Stratix IV Devices chapter.
February 2011
SIV54002-1.5
相关PDF资料 |
PDF描述 |
|---|---|
| 93C56CT-E/MNY | IC EEPROM SER 2K 256X8 8TDFN |
| EP4SGX530NF45C2N | IC STRATIX IV FPGA 530K 1932FBGA |
| 93C56BT-E/MNY | IC EEPROM SER 2K 128X16 8TDFN |
| EP4SGX530NF45I3N | IC STRATIX IV FPGA 530K 1932FBGA |
| 93C56AT-E/MNY | IC EEPROM SER 2K 256X8 8TDFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4SE820H35C3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SE820H35C4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SE820H35C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SE820H35I3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SE820H35I3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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