参数资料
| 型号： | EP4SGX110FF35I3 |
| 厂商： | Altera |
| 文件页数： | 16/82页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 110K 1152FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB数： | 4224 |
| 逻辑元件/单元数： | 105600 |
| RAM 位总计： | 9793536 |
| 输入/输出数： | 372 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 1152-BBGA |
| 供应商设备封装： | 1152-FBGA（27x27） |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–15
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Power Consumption
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus II PowerPlay Power Analyzer feature.
1 You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Stratix IV core and periphery
blocks for commercial, industrial, and military grade devices.
The final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. There are no designations on finalized
tables.
BLVDS (8)
2.375 2.5
2.625 100
—
Notes to Table 1–22:
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–16.
(3) Differential clock inputs in column I/O are powered by VCC_CLKIN which requires 2.5 V. Differential inputs that are not on clock pins in column I/O are
powered by VCCPD which requires 2.5 V. All differential inputs in row I/O banks are powered by VCCPD which requires 2.5V.
(4) RL range: 90
RL 110 .
(5) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 1.0 V VIN 1.6 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is zero V VIN 1.85 V.
(6) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 0.85 V VIN 1.75 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is 0.45 V VIN 1.95 V.
(7) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins.
(8) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interfaces in Supported Altera Device
Table 1–22. Differential I/O Standard Specifications (1), (2) (Part 2 of 2)
I/O
Standard
VCCIO (V) (3)
VID (mV)
VICM(DC) (V)
VOD (V) (4)
VOCM (V) (4)
Min
Typ
Max
Min Condition Max
Min
Condition
Max
Min
Typ Max
Min
Typ
Max
相关PDF资料 |
PDF描述 |
|---|---|
| EP4SGX110FF35C2X | IC STRATIX IV FPGA 110K 1152FBGA |
| EP4SGX110HF35I3 | IC STRATIX IV FPGA 110K 1152FBGA |
| RBB108DHAR | CONN EDGECARD 216PS R/A .050 DIP |
| 1658686-2 | CONN D-SUB SOCKET 22-28AWG GOLD |
| HMC44DRYI | CONN EDGECARD 88POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4SGX110FF35I3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 4224 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX110FF35I4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 4224 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX110FF35I4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 4224 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX110HF35C2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX110HF35C2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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