参数资料
| 型号： | EP4SGX230KF40C4 |
| 厂商： | Altera |
| 文件页数： | 73/82页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 230K 1517FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB数： | 9120 |
| 逻辑元件/单元数： | 228000 |
| RAM 位总计： | 17544192 |
| 输入/输出数： | 744 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1517-BBGA |
| 供应商设备封装： | 1517-FBGA（40x40） |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–67
Glossary
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Document Revision History
Table 1–55 lists the revision history for this chapter.
V
VCM(DC)
DC Common mode input voltage.
VICM
Input Common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH(AC)
High-level AC input voltage
VIH(DC)
High-level DC input voltage
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL(AC)
Low-level AC input voltage
VIL(DC)
Low-level DC input voltage
VOCM
Output Common mode voltage—The common mode of the differential signal at the
transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
Differential input voltage
VX
Input differential cross point voltage
VOX
Output differential cross point voltage
W
W
High-speed I/O block: Clock Boost Factor
X, Y, Z
——
Table 1–54. Glossary Table (Part 4 of 4)
Letter
Subject
Definitions
Table 1–55. Document Revision History (Part 1 of 3)
Date
Version
Changes
March 2014
5.8
■ Added note to Table 1–49.
■ Updated D6 row in Table 1–52.
January 2014
5.7
■ Updated Table 1–42.
December 2013
5.6
■ Updated Table 1–23 and Table 1–24.
November 2013
5.5
■ Updated Table 1–23 and Table 1–24.
November 2013
5.4
■ Updated Table 1–42, Table 1–23, and Table 1–24.
July 2012
5.3
■ Added Table 1–5 and Table 1–40.
■ Updated Table 1–15, Table 1–22, Table 1–23, Table 1–30, Table 1–33, Table 1–35,
Table 1–36, Table 1–39, Table 1–42 and Table 1–51.
■ Removed “Schmitt Trigger Input” section.
December 2011
5.2
■ Added Figure 1–7.
■ Updated Table 1–22 and Table 1–41.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4SGX230KF40C4ES | 制造商:Altera Corporation 功能描述:IC FPGA 744 I/O 1517FBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1517FBGA |
| EP4SGX230KF40C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 9120 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX230KF40C4NES | 制造商:Altera Corporation 功能描述:IC FPGA 744 I/O 1517FBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1517FBGA |
| EP4SGX230KF40I3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 9120 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX230KF40I3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 9120 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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