参数资料
型号: EP4SGX70HF35C3
厂商: Altera
文件页数: 7/82页
文件大小: 0K
描述: IC STRATIX IV FPGA 70K 1152FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 3
系列: Stratix® IV GX
LAB/CLB数: 2904
逻辑元件/单元数: 72600
RAM 位总计: 7564880
输入/输出数: 488
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 1152-BBGA
供应商设备封装: 1152-FBGA(27x27)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–7
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Handbook.
I/O Pin Leakage Current
Table 1–9 lists the Stratix IV I/O pin leakage current specifications.
VCCR_R
Receiver power (right side)
1.15
1.2
1.25
V
VCCT_L
Transmitter power (left side)
1.15
1.2
1.25
V
VCCT_R
Transmitter power (right side)
1.15
1.2
1.25
V
VCCL_GXBLn (3)
Transceiver clock power (left side)
1.15
1.2
1.25
V
VCCL_GXBRn (3)
Transceiver clock power (right side)
1.15
1.2
1.25
V
VCCH_GXBLn (3)
Transmitter output buffer power (left side)
1.33
1.4
1.47
V
VCCH_GXBRn (3)
Transmitter output buffer power (right side)
1.33
1.4
1.47
V
Notes to Table 1–8:
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(3) n = 0, 1, 2, or 3.
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 2 of 2) (1), (2)
Symbol
Description
Minimum
Typical
Maximum
Unit
Table 1–9. I/O Pin Leakage Current for Stratix IV Devices (1)
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0V to VCCIOMAX
-20
20
A
IOZ
Tri-stated I/O pin
VO = 0V to VCCIOMAX
-20
20
A
Note to Table 1–9:
(1) VREF current refers to the input pin leakage current.
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EP4SGX70HF35C4 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 2904 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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