参数资料
| 型号： | EP4SGX70HF35I4 |
| 厂商： | Altera |
| 文件页数： | 10/82页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 70K 1152FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB数： | 2904 |
| 逻辑元件/单元数： | 72600 |
| RAM 位总计： | 7564880 |
| 输入/输出数： | 488 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 1152-BBGA |
| 供应商设备封装： | 1152-FBGA（27x27） |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–10
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 1–13 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 1–13 to determine the OCT variation after power-up calibration
and Equation 1–1 to determine the OCT variation without re-calibration.
Table 1–13 lists the OCT variation after the power-up calibration.
Pin Capacitance
Table 1–14 lists the Stratix IV device family pin capacitance.
Notes to Equation 1–1:
(1) The ROCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature
and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3)
T is the variation of temperature with respect to the temperature at power-up.
(4)
V is the variation of voltage with respect to the V
CCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 1–13. OCT Variation after Power-Up Calibration (1)
Symbol
Description
VCCIO (V)
Typical
Unit
dR/dV
OCT variation with voltage without
re-calibration
3.0
0.0297
%/mV
2.5
0.0344
1.8
0.0499
1.5
0.0744
1.2
0.1241
dR/dT
OCT variation with temperature
without re-calibration
3.0
0.189
%/°C
2.5
0.208
1.8
0.266
1.5
0.273
1.2
0.317
Note to Table 1–13:
(1) Valid for VCCIO range of ±5% and temperature range of 0° to 85°C.
ROCT
RSCAL 1
dR
dT
-------
T
dR
dV
-------
V
+
=
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 1 of 2)
Symbol
Description
Value
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
4
pF
CIOLR
Input capacitance on the left and right I/O pins
4
pF
CCLKTB
Input capacitance on the top and bottom non-dedicated clock input pins
4
pF
CCLKLR
Input capacitance on the left and right non-dedicated clock input pins
4
pF
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