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参数资料
| 型号： | EP610 |
| 厂商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 经典系列可编程逻辑器件（典型可编程逻辑器件系列器件） |
| 文件页数： | 1/15页 |
| 文件大小： | 227K |
| 代理商： | EP610 |
Altera Corporation
969
Understanding MAX 5000 &
Classic Timing
May 1999, ver. 3
Application Note 78
A-AN-078-03
Introduction
Altera
devices provide performance that is consistent from simulation to
application. Before programming a device, you can determine the worst-
case timing delays for any design. You can calculate propagation delays
either with the MAX+PLUS
II Timing Analyzer or with the timing
models given in this application note and the timing parameters listed in
individual device data sheets. Both methods yield the same results.
This application note defines internal and external timing parameters,
and illustrates the timing models for the MAX
5000 (including
MAX 5000A), and Classic
device families.
Familiarity with device architecture and characteristics is assumed. Refer
to the device family data sheets in this data book for complete
descriptions of the architectures, and for the specific values of the timing
parameters listed in this application note.
Internal Timing
Parameters
Within a device, the timing delays contributed by individual architectural
elements are called internal timing parameters, which cannot be
measured explicitly. All internal timing parameters are shown in italic
type. The following section defines the internal timing parameters for
MAX 5000 and Classic devices, and applies to both device families unless
otherwise indicated. Classic devices include the EP610, EP610I, EP910,
EP910I , and EP1810 devices only.
t
IN
The time required for a dedicated input pin to drive the true and
complement data input signal into the logic array(s).
t
IO
I/O input pad and buffer delay. The
t
IO
delay applies to I/O
pins used as inputs. In multi-LAB MAX 5000 devices,
t
IO
is the
delay from the I/O pin to the PIA. In MAX 5000 devices with a
single logic array block (LAB),
t
IO
is the delay from the I/O pin
to the logic arrays. In Classic devices,
t
IO
is the delay added to
t
IN
.
t
PIA
Programmable interconnect array (PIA) delay. The delay
incurred by signals that require routing through the PIA.
Multi-LAB MAX 5000 devices only.
相关PDF资料 |
PDF描述 |
|---|---|
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| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP-610419-2.5-9 | 功能描述:打印机 Label ID 41.9x61mm EP RoHS:否 制造商:Seiko Instruments 产品:Printer 电源电压: 每行点数:9 x 320 打印速度:52.5 cps, 80 cps 纸张宽度:112 mm |
| EP610ALC-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP PLD |
| EP610ALC-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP PLD |
| EP610ALC-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP PLD |
| EP610ALC-7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP PLD |
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