参数资料
| 型号： | EP7311-CV-90 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 35/42页 |
| 文件大小： | 0K |
| 描述： | IC ARM720T MCU 90MHZ 208-LQFP |
| 标准包装： | 36 |
| 系列： | EP7 |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 32-位 |
| 速度： | 90MHz |
| 连通性： | 编解码器，EBI/EMI，IrDA，键盘，多媒体编解码器，SPI/Microwire1，UART/USART |
| 外围设备： | LCD，LED，MaverickKey，PWM |
| 输入/输出数： | 27 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 56K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.3 V ~ 2.7 V |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-LQFP |
| 包装： | 托盘 |
| 其它名称： | 598-1225 |
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40
4341H–MP3–10/07
AT8xC51SND2C/MP3B
9.2
External Interrupts
9.2.1
INT1:0 Inputs
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-
triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register
as shown in Figure 9-2. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is
negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1)
in IEN0. Events on INTn set the interrupt request flag IEn in TCON register. If the interrupt is
edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service
routine. If the interrupt is level-triggered, the interrupt service routine must clear the request flag
and the interrupt must be deasserted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low level sig-
nals as detailed in section “Exiting Power-down Mode”, page 50.
Figure 9-2.
INT1:0 Input Circuitry
9.2.2
KIN0 Inputs
External interrupts KIN0 provides the capability to connect a keyboard. For detailed information
on this inputs, refer to section “Keyboard Interface”, page 204.
9.2.3
Input Sampling
External interrupt pins (INT1:0 and KIN0) are sampled once per peripheral cycle (6 peripheral
clock periods) (see Figure 9-3). A level-triggered interrupt pin held low or high for more than 6
peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode)
guarantees detection. Edge-triggered external interrupts must hold the request pin low for at
least 6 peripheral clock periods.
Figure 9-3.
Minimum Pulse Timings
0
1
INT0/1
IT0/1
TCON.0/2
EX0/1
IEN0.0/2
INT0/1
Interrupt
Request
IE0/1
TCON.1/3
Edge-Triggered Interrupt
Level-Triggered Interrupt
1 cycle
>
1 Peripheral Cycle
1 cycle
>
1 Peripheral Cycle
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP7311-CV-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-EB-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-ER-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-EV-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-IB | 功能描述:音频片上系统 - SoC IC Ultra Low PWR Hi Perf SOC w/LCD RoHS:否 制造商:Cirrus Logic |
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