参数资料
| 型号： | EP7311-CV |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 19/42页 |
| 文件大小： | 0K |
| 描述： | IC ARM720T MCU 74MHZ 208-LQFP |
| 标准包装： | 36 |
| 系列： | EP7 |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 32-位 |
| 速度： | 74MHz |
| 连通性： | 编解码器，EBI/EMI，IrDA，键盘，多媒体编解码器，SPI/Microwire1，UART/USART |
| 外围设备： | LCD，LED，MaverickKey，PWM |
| 输入/输出数： | 27 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 56K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.3 V ~ 2.7 V |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-LQFP |
| 包装： | 托盘 |
| 其它名称： | 598-1224 |
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26
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 7-3 shows the structure of the external address bus. P0 carries address A7:0 while P2
carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 7-3 describes the exter-
nal memory interface signals.
Figure 7-3.
External Data Memory Interface Structure
Table 7-3.
External Data Memory Interface Signals
7.2.2
Page Access Mode
The AT8xC51SND2C implement a feature called Page Access that disables the output of DPH
on P2 when executing MOVX @DPTR instruction. Page Access is enable by setting the DPH-
DIS bit in AUXR register.
Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In this case,
software modifies intensively EXTRAM bit to select access to ERAM or XRAM and must save it
if used in interrupt service routine. Page Access allows external access above 00FFh address
without generating DPH on P2. Thus ERAM is accessed using MOVX @Ri or MOVX @DPTR
with DPTR < 0100h, < 0200h, < 0400h or < 0800h depending on the XRS1:0 bits value. Then
XRAM is accessed using MOVX @DPTR with DPTR ≥ 0800h regardless of XRS1:0 bits value
while keeping P2 for general I/O usage.
7.2.3
External Bus Cycles
This section describes the bus cycles the AT8xC51SND2C executes to read (see Figure 7-4),
and write data (see Figure 7-5) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period
Signal
Name
Type
Description
Alternate
Function
A15:8
O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
-
RD
O
Read
Read signal output to external data memory.
P3.7
WR
O
Write
Write signal output to external memory.
P3.6
RAM
PERIPHERAL
AT8xC51SND2C
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
WR
OE
RD
WR
Latch
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP7311-CV-90 | 功能描述:音频片上系统 - SoC IC Ultra Lw Pwr Hi Perf SOC w/LCD RoHS:否 制造商:Cirrus Logic |
| EP7311-CV-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-EB-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-ER-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7311-EV-C | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
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