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| 型号： | EP9302-IQZ |
| 厂商： | Cirrus Logic, Inc. |
| 英文描述： | High-speed ARM9 System-on-chip Processor with MaverickCrunch |
| 中文描述： | 高速ARM9的系统级芯片处理器MaverickCrunch |
| 文件页数： | 7/42页 |
| 文件大小： | 302K |
| 代理商： | EP9302-IQZ |
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DS653PP3
Copyright 2005 Cirrus Logic (All Rights Reserved)
7
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
Interfaces to an off-chip PHY through industry-
standard Media-independent Interface (MII)
Serial Interfaces (SPI, I
2
S, and AC ’97)
The Serial Peripheral Interface (SPI) port can be
configured as a master or a slave, supporting the
National
Semiconductor
,
Instruments
signaling protocols.
Motorola
,
and
Texas
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I
2
S port
supports stereo 24-bit audio.
These ports are multiplexed so that the I
2
S port will take
over either the AC'97 pins or the SPI pins.
Normal Mode: One SPI Port and one AC’97 Port
I
2
S on SSP Mode: One AC’97 Port and one I
2
S Port
I
2
S on AC’97 Mode: One SPI Port and one I
2
S Port
Note:
I
2
S may not be output on AC’97 and SSP ports at the
same time.
12-bit Analog-to-digital Converter (ADC)
The ADC block consists of a 12-bit analog-to-digital
converter with a analog input multiplexer. The multiplexer
can select to measure battery voltage and other
miscellaneous voltages on the external measurement
pins. Features include:
5 external pins for ADC measurement
Measurement pin input range: 0 to 3.3 V.
ADC-conversion-complete interrupt signal
Table C. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
Pin Description
MDC
Management Data Clock
MDIO
Management Data I / O
RXCLK
Receive Clock
MIIRXD[3:0]
Receive Data
RXDVAL
Receive Data Valid
RXERR
Receive Data Error
TXCLK
Transmit Clock
MIITXD[3:0]
Transmit Data
TXEN
Transmit Enable
TXERR
Transmit Error
CRS
Carrier Sense
CLD
Collision Detect
Table D. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I
2
S on SSP
Mode
I
2
S on AC'97
Mode
Pin
Description
Pin Description
Pin Description
SCLK1
SPI Bit Clock
I2S Serial Clock
SPI Bit Clock
SFRM1
SPI Frame Clock I2S Frame Clock
SPI Frame Clock
SSPRX1
SPI Serial Input
I2S Serial Input
SPI Serial Input
SSPTX1
SPI Serial
Output
I2S Serial Output
SPI Serial Output
(No I2S Master
Clock)
ARSTn
AC'97 Reset
AC'97 Reset
I2S Master Clock
ABITCLK AC'97 Bit Clock
AC'97 Bit Clock
I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input
I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial Output I2S Serial Output
Table E. 12-bit Analog-to-Digital Converter Pin Assignments
Pin Mnemonic
Pin Description
ADC[0] (Ym, pin 135)
External Analog Measurement Input
ADC[1] (sXp, pin 134)
External Analog Measurement Input
ADC[2] (sXm, pin 133)
External Analog Measurement Input
ADC[3] (sYp, pin 132)
External Analog Measurement Input
ADC[4] (sYm, pin 131)
External Analog Measurement Input
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