参数资料
| 型号： | EP9307-IR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC ARM920T MCU 200MHZ 272-TFBGA |
| 标准包装： | 119 |
| 系列： | EP9 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 200MHz |
| 连通性： | EBI/EMI，以太网，I²C，IrDA，键盘/触摸屏，SPI，UART/USART，USB |
| 外围设备： | AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT |
| 输入/输出数： | 14 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 32K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 272-TFBGA |
| 包装： | 托盘 |
| 配用： | 598-1133-ND - KIT DEVELOPMENT EP9307 ARM9 |
| 其它名称： | 598-1255 |
ER667E2B
9
Workaround
Insure that this kind of sequence of instructions does not occur. Note that adding a small number of
intervening instructions may not be sufficient to avoid this problem. If such a sequence must occur, insure
that the first and third instructions are sufficiently far apart in the instruction stream by placing five other
instructions between them:
cfadd32
c0, c1, c2
nop
; inserted extra instruction here
nop
; inserted extra instruction here
cfsub32ne
c0, c3, c4
; assume this does not execute
nop
; inserted extra instruction here
nop
; inserted extra instruction here
nop
; inserted extra instruction here
cfstr32
c0, [r2, #0x0]
The five intervening instructions need not be nops and may appear before or after the second instruction.
Note that it is the instruction stream as executed by the processor, not the instructions as they appear in the
source code, which is relevant. Hence, cases where the program flow changes between the first and third
instruction must be considered.
To avoid this error when entering exception and interrupt handlers, the first five instructions of an exception
or interrupt handler should not be coprocessor instructions.
Description 3
Under certain circumstances, data in coprocessor general purpose registers or in memory may be
corrupted. The error appears as follows.
1) Let the first instruction be a serialized instruction that does not execute1. For an instruction to be serial-
ized, at least one of the following must be true:
- The processor must be operating in serialized2 mode.
- The instruction must move to or from the DSPSC (either cfmv32sc or cfmvsc32).
2) Let the immediately following instruction be a two-word coprocessor load or store4.
In the case of a load, only the lower 32 bits (the first word) will be loaded into the target register. For example:
cfadd32ne
c0, c1, c2
; assume this does not execute
cfldr64
c3, [r2, #0x0]
The lower 32 bits of c3 will correctly become what is at the memory address in r2, but the upper 32 bits of
c3 will not become what is at address r2 + 0x4.
In the case of a store, only the lower 32 bits (the first word) will be stored into memory. For example:
cfadd32ne
c4, c5, c6
; assume this does not execute
cfstr64
c3, [r2, #0x0]
The lower 32 bits of c3 will be correctly written to the memory address in r2, but the upper 32 bits of c3 will
not be written.
(Continued)
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