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参数资料
| 型号： | EPC1213PC8 |
| 厂商： | Altera |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 1MBIT 8-DIP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 100 |
| 系列： | EPC |
| 可编程类型： | OTP |
| 存储容量： | 212kb |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 配用： | PLMJ1213-ND - PROGRAMMER ADAPTER 20 PIN J-LEAD |
| 其它名称： | 544-1222-5 |
Timing Information
Page 17
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
Table 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V.
Table 10 lists the timing parameters when using EPC1, EPC2, and EPC1441 devices at
5.0 V.
Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V
Symbol
Parameter
Min
Typ
Max
Units
tPOR
POR delay (1)
——
200
ms
tOEZX
OE
high to DATA output enabled
—
80
ns
tCE
OE
high to first rising edge on DCLK
——
300
ns
tDSU
Data
setup time before rising edge on DCLK
30
—
ns
tDH
Data
hold time after rising edge on DCLK
0—
—
ns
tCO
DCLK
to DATA out
—
30
ns
tCDOE
DCLK
to DATA enable/disable
—
30
ns
fCLK
DCLK
frequency
2
4
10
MHz
tMCH
DCLK
high time for the first device in the configuration chain
50
125
250
ns
tMCL
DCLK
low time for the first device in the configuration chain
50
125
250
ns
tSCH
DCLK
high time for subsequent devices
50
—
ns
tSCL
DCLK
low time for subsequent devices
50
—
ns
tCASC
DCLK
rising edge to nCASC
—
25
ns
tCCA
nCS
to nCASC cascade delay
—
15
ns
tOEW
OE
low pulse width (reset) to guarantee counter reset
100
—
ns
tOEC
OE
low (reset) to DCLK disable delay
—
30
ns
tNRCAS
OE
low (reset) to nCASC delay
—
30
ns
Note to Table 9:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
tPOR
POR delay (1)
——
200
ms
tOEZX
OE
high to DATA output enabled
—
50
ns
tCE
OE
high to first rising edge on DCLK
——
200
ns
tDSU
Data
setup time before rising edge on DCLK
30
—
ns
tDH
Data
hold time after rising edge on DCLK
0—
—
ns
tCO
DCLK
to DATA out
—
20
ns
tCDOE
DCLK
to DATA enable/disable
—
20
ns
fCLK
DCLK
frequency
6.7
10
16.7
MHz
tMCH
DCLK
high time for the first device in the configuration chain
30
50
75
ns
tMCL
DCLK
low time for the first device in the configuration chain
30
50
75
ns
tSCH
DCLK
high time for subsequent devices
30
—
ns
tSCL
DCLK
low time for subsequent devices
30
—
ns
tCASC
DCLK
rising edge to nCASC
—
20
ns
tCCA
nCS
to nCASC cascade delay
—
10
ns
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|---|---|
| EPC1213PC-8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Configuration EPROM |
| EPC1213PI8 | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 212Kb 6 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC1213PI-8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Configuration EPROM |
| EPC-12179 | 制造商:Artisan Controls Corporation 功能描述:LIGHTING CONTROLLER |
| EPC-12457 | 制造商:Artisan Controls Corporation 功能描述:Timer |
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