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参数资料
| 型号： | EPC8xxx |
| 厂商： | Altera Corporation |
| 英文描述： | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| 中文描述： | 2。增强型配置器件（EPC4，EPC8 |
| 文件页数： | 2/36页 |
| 文件大小： | 421K |
| 代理商： | EPC8XXX |
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2–2
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Functional Description
■
Hardware compliant with IEEE Std. 1532 in-system
programmability (ISP) specification
Supports ISP via Jam Standard Test and Programming Language
(STAPL)
Supports Joint Test Action Group (JTAG) boundary scan
nINIT_CONF
pin allows private JTAG instruction to initiate FPGA
configuration
Internal pull-up resistor on
nINIT_CONF
always enabled
User programmable weak internal pull-up resistors on
nCS
and
OE
pins
Internal weak pull-up resistors on external flash interface address
and control lines, bus hold on data lines
Standby mode with reduced power consumption
■
■
■
■
■
■
■
f
For more information on FPGA configuration schemes and advanced
features, refer to the appropriate FPGA family chapter in the
Configuration
Handbook
.
Functional
Description
The Altera enhanced configuration device is a single-device, high-speed,
advanced configuration solution for very high-density FPGAs. The core
of an enhanced configuration device is divided into two major blocks, a
configuration controller and a flash memory. The flash memory is used to
store configuration data for systems made up of one or more Altera
FPGAs. Unused portions of the flash memory can be used to store
processor code or data that can be accessed via the external flash interface
after FPGA configuration is complete.
1
The external flash interface is currently supported in the EPC16
and EPC4 devices. For information on using this feature in the
EPC8 device, contact Altera Applications.
The enhanced configuration device has a 3.3-V core and I/O interface.
The controller chip is a synchronous system that implements the various
interfaces and features.
Figure 2–1
shows a block diagram of the
enhanced configuration device. The controller chip features three
separate interfaces:
■
A configuration interface between the controller and the Altera
FPGA(s)
A JTAG interface on the controller that enables in-system
programmability (ISP) of the flash memory
An external flash interface that the controller shares with an external
processor, or FPGA implementing a Nios
embedded processor
(interface available after ISP and configuration)
■
■
相关PDF资料 |
PDF描述 |
|---|---|
| EPC8QC100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC8QI100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC16xxx | 435882001 |
| EPC4QC100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC4QI100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
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