- 您现在的位置：买卖IC网 > PDF目录362744 > EPCS1 (Altera Corporation) Serial Configuration Devices PDF资料下载
参数资料
| 型号： | EPCS1 |
| 厂商： | Altera Corporation |
| 英文描述： | Serial Configuration Devices |
| 中文描述： | 串行配置器件 |
| 文件页数： | 15/32页 |
| 文件大小： | 236K |
| 代理商： | EPCS1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
Altera Corporation
July 2004
Core Version a.b.c variable
4–15
Configuration Handbook, Volume 2
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Figure 4–9. Read Status Operation Timing Diagram
Write Status Operation
The write status operation code is
b'0000 0001
, with the MSB listed
first. Use the write status operation to set the status register block
protection bits. The write status operation has no effect on the other bits.
Therefore, designers can implement this operation to protect certain
memory sectors, as defined in
Tables 4–9
and
4–10
. After setting the block
protect bits, the protected memory sectors are treated as read-only
memory. Designers must execute the write enable operation before the
write status operation so the device sets the status register’s write enable
latch bit to 1.
The write status operation is implemented by driving
nCS
low, followed
by shifting in the write status operation code and one data byte for the
status register on the
ASDI
pin.
Figure 4–10
shows the timing diagram for
the write status operation.
nCS
must be driven high after the eighth bit of
the data byte has been latched in, otherwise, the write status operation is
not executed.
Immediately after
nCS
is driven high, the device initiates the self-timed
write status cycle. The self-timed write status cycle usually takes 5 ms for
both serial configuration devices and is guaranteed to be less than 15 ms
(see t
WS
in
Table 4–12
). Designers must account for this delay to ensure
that the status register is written with desired block protect bits.
Alternatively, you can check the write in progress bit in the status register
by executing the read status operation while the self-timed write status
cycle is in progress. The write in progress bit is 1 during the self-timed
write status cycle, and is 0 when it is complete.
nCS
DCLK
ASDI
DATA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7
6
5
4
3
2
1
0
7
2
1
0
7
6
5
4
3
Operation Code
MSB
MSB
Status Register Out
Status Register Out
High Impedance
相关PDF资料 |
PDF描述 |
|---|---|
| EPCS16 | Serial Configuration Devices |
| EPCS16SI16N | Serial Configuration Devices |
| EPCS1SI8N | Serial Configuration Devices |
| EPCS4 | Serial Configuration Devices |
| EPCS4SI8N | Serial Configuration Devices |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPCS1_1 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Serial Configuration Devices |
| EPCS128 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Serial Configuration Devices |
| EPCS128SI16N | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 128Mb 40 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPCS16 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Serial Configuration Devices |
| EPCS16SI16N | 功能描述:IC CONFIG DEVICE 16MBIT 16-SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:EPCS 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。