参数资料
型号: EPF10K100EFC256-3
厂商: Altera
文件页数: 8/100页
文件大小: 0K
描述: IC FLEX 10KE FPGA 100K 256-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 90
系列: FLEX-10KE®
LAB/CLB数: 624
逻辑元件/单元数: 4992
RAM 位总计: 49152
输入/输出数: 191
门数: 257000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 256-BGA
供应商设备封装: 256-FBGA(17x17)
其它名称: 544-2192
Altera Corporation
15
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive write
enable, read enable, and clock enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write enable, read enable, clear, clock, and clock enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outputs (see Figures 2 and 4). The column interconnect, which is adjacent
to the EAB, has twice as many channels as other columns in the device.
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the FLEX 10KE architecture, facilitating
efficient routing with optimum device utilization and high performance
(see Figure 7).
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EPF10K100EFC484-1DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
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