参数资料
型号: EPF10K10ATI144-3N
厂商: Altera
文件页数: 56/128页
文件大小: 0K
描述: IC FLEX 10KA FPGA 10K 144-TQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 180
系列: FLEX-10K®
LAB/CLB数: 72
逻辑元件/单元数: 576
RAM 位总计: 6144
输入/输出数: 102
门数: 31000
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
Altera Corporation
33
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. The
internally generated signal can drive the global signal, providing the same
low-skew, low-delay characteristics for an internally generated signal as
for a signal driven by an input. This feature is ideal for internally
generated clear or clock signals with high fan-out. When a global signal is
driven by internal logic, the dedicated input pin that drives that global
signal cannot be used. The dedicated input pin should be driven to a
known logic state (such as ground) and not be allowed to float.
When the chip-wide output enable pin is held low, it will tri-state all pins
on the device. This option can be set in the Global Project Device Options
menu. Additionally, the registers in the IOE can be reset by holding the
chip-wide reset pin low.
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel. See Figure 14.
Figure 14. FLEX 10K Row-to-IOE Connections
n
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive up to two
row channels.
IOE8
IOE1
m
Row FastTrack
Interconnect
n
The values for m and n are provided in Table 10.
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