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参数资料
型号： EPF10K20RC208-3
厂商： Altera
文件页数： 38/128页
文件大小： 0K
描述： IC FLEX 10K FPGA 20K 208-RQFP
产品培训模块： Three Reasons to Use FPGA's in Industrial Designs
产品变化通告： Package Change 30/Jun/2010
标准包装： 48
系列： FLEX-10K®
LAB/CLB数： 144
逻辑元件/单元数： 1152
RAM 位总计： 12288
输入/输出数： 147
门数： 63000
电源电压： 4.75 V ~ 5.25 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 208-BFQFP 裸露焊盘
供应商设备封装： 240-RQFP（32x32）
产品目录页面： 603 (CN2011-ZH PDF)
其它名称： 544-2207
Altera Corporation
17
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the FLEX 10K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.7 ns per LE. Cascade
chain logic can be created automatically by the Compiler during design
processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50 device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
nineteenth LAB). This break is due to the EAB’s placement in the middle
of the row.
Figure 8 shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. The LE delay is as low as 1.6 ns; the
cascade chain delay is as low as 0.7 ns. With the cascade chain, 3.7 ns is
needed to decode a 16-bit address.
Figure 8. Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4
n-1)..(4n-4)]
d[3..0]
d[7..4]
d[(4
n-1)..(4n-4)]
LE
n
LE1
LE2
LE
n
LUT
AND Cascade Chain
OR Cascade Chain
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相关代理商/技术参数
参数描述
EPF10K20RC208-3N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 144 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K20RC2084 制造商:ALTERA 功能描述:New
EPF10K20RC208-4 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 144 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K20RC208-4N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 144 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K20RC240-3 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 144 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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