参数资料
型号: EPF10K20RI240-4
厂商: Altera
文件页数: 13/128页
文件大小: 0K
描述: IC FLEX 10K FPGA 20K 240-RQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
产品变化通告: Package Change 30/Jun/2010
标准包装: 24
系列: FLEX-10K®
LAB/CLB数: 144
逻辑元件/单元数: 1152
RAM 位总计: 12288
输入/输出数: 189
门数: 63000
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 240-BFQFP 裸露焊盘
供应商设备封装: 240-RQFP(32x32)
其它名称: 544-2215
Altera Corporation
11
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256
× 8 RAM blocks can be combined to form a
256
× 16 RAM block; two 512 × 4 blocks of RAM can be combined to form
a 512
× 8RAM block. See Figure 3.
Figure 3. Examples of Combining EABs
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera’s software automatically combines
EABs to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks can be used for the EAB inputs and outputs. Registers can
be independently inserted on the data input, EAB output, or the address
and WE inputs. The global signals and the EAB local interconnect can drive
the WE signal. The global signals, dedicated clock pins, and EAB local
interconnect can drive the EAB clock signals. Because the LEs drive the
EAB local interconnect, the LEs can control the WE signal or the EAB clock
signals.
Each EAB is fed by a row interconnect and can drive out to row and
column interconnects. Each EAB output can drive up to two row channels
and up to two column channels; the unused row channel can be driven by
other LEs. This feature increases the routing resources available for EAB
outputs. See Figure 4.
512
× 4
512
× 4
256
× 8
256
× 8
256
× 16
512
× 8
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