参数资料
型号: EPF10K30
厂商: Altera Corporation
英文描述: Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列)
中文描述: 嵌入式可编程逻辑系列(FLEX10K嵌入式可编程逻辑系列)
文件页数: 17/138页
文件大小: 2115K
代理商: EPF10K30
Altera Corporation
17
FLEX 10K Embedded Programmable Logic Family Data Sheet
Cascade Chain
With the cascade chain, the FLEX 10K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical
AND
or logical
OR
(via De Morgan’s inversion) to connect the outputs of
adjacent LEs. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.7 ns per LE. Cascade
chain logic can be created automatically by the MAX+PLUS II Compiler
during design processing, or manually by the designer during design
entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50 device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
nineteenth LAB). This break is due to the EAB’s placement in the middle
of the row.
Figure 8
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. These examples show functions of 4
n
variables implemented with
n
LEs. The LE delay is as low as 1.6 ns; the
cascade chain delay is as low as 0.7 ns. With the cascade chain, 3.7 ns is
needed to decode a 16-bit address.
Figure 8. Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4n-1)..(4n-4)]
d[3..0]
d[7..4]
d[(4n-1)..(4n-4)]
LEn
LE1
LE2
LEn
LUT
LUT
LUT
LUT
AND Cascade Chain
OR Cascade Chain
相关PDF资料
PDF描述
EPF10K200E Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列)
EPF10K30E Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列)
EPF10K50S Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列)
EPF10K130E Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列)
EPF10K200S Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列)
相关代理商/技术参数
参数描述
EPF10K30A 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Embedded Programmable Logic Device Family
EPF10K30ABC3561 制造商:ALTERA 功能描述:*
EPF10K30ABC356-1 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K30ABC3562 制造商:ALTERA 功能描述:New
EPF10K30ABC356-2 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256