参数资料
型号: EPF10K30AQC240-2N
厂商: Altera
文件页数: 62/128页
文件大小: 0K
描述: IC FLEX 10KA FPGA 30K 240-PQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 24
系列: FLEX-10K®
LAB/CLB数: 216
逻辑元件/单元数: 1728
RAM 位总计: 12288
输入/输出数: 189
门数: 69000
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 240-BFQFP
供应商设备封装: 240-PQFP(32x32)
其它名称: 544-1940
EPF10K30AQC240-2N-ND
Altera Corporation
39
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of approximately
2.9 ns. The fast slew rate should be used for speed-critical outputs in
systems that are adequately protected against noise. Designers can specify
the slew rate on a pin-by-pin basis during design entry or assign a default
slew rate to all pins on a device-wide basis. The slow slew rate setting
affects only the falling edge of the output.
Open-Drain Output Option
FLEX 10K devices provide an optional open-drain (electrically equivalent
to an open-collector) output for each I/O pin. This open-drain output
enables the device to provide system-level control signals (e.g., interrupt
and write enable signals) that can be asserted by any of several devices. It
can also provide an additional wired-OR plane. Additionally, the Altera
software can convert tri-state buffers with grounded data inputs to open-
drain pins automatically.
Open-drain output pins on FLEX 10K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin is
inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain
pin will only drive low or tri-state; it will never drive high. The rise time
is dependent on the value of the pull-up resistor and load impedance. The
IOL current specification should be considered when selecting a pull-up
resistor.
Output pins on 5.0-V FLEX 10K devices with VCCIO = 3.3 V or 5.0 V (with
a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input
pins. In this case, the pull-up transistor will turn off when the pin voltage
exceeds 3.3 V. Therefore, the pin does not have to be open-drain.
MultiVolt I/O Interface
The FLEX 10K device architecture supports the MultiVolt I/O interface
feature, which allows FLEX 10K devices to interface with systems of
differing supply voltages. These devices have one set of VCC pins for
internal operation and input buffers (VCCINT) and another set for I/O
output drivers (VCCIO).
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EPF10K30AQC240-3N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K30AQI208-3 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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EPF10K30AQI240-3 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256