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参数资料
型号： EPF10K30EFC256-2X
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 现场可编程门阵列（FPGA）
文件页数： 9/120页
文件大小： 1901K
代理商： EPF10K30EFC256-2X
106
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
All pins that are not listed are user I/O pins.
(2)
EPF10K50E, EPF10K100E, and EPF10K100B devices are pin-compatible with the EPF10K130E devices in the same
package if pins 20, 76, and 159 are connected to VCCINT. The MAX+PLUS II software performs this function
automatically when future migration is set.
(3)
EPF10K50E, EPF10K100E, and EPF10K100B devices are pin-compatible with the EPF10K200E devices in the same
package if pins 20, 40, 76, 139, 159, 187, and 225 are connected to VCCINT. The MAX+PLUS II software performs this
function automatically when future migration is set.
(4)
This pin is a dedicated pin; it is not available as a user I/O pin.
(5)
This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(6)
This pin can be used as a user I/O pin after configuration.
(7)
This pin is tri-stated in user mode.
(8)
The optional JTAG pin TRST is not used in the 144-pin TQFP package.
(9)
This pin drives the ClockLock and ClockBoost circuitry.
(10) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry
is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high if a periodic
clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin.
(11) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power
and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the
rest of the device. If the ClockLock or ClockBoost circuitry is not used, this power or ground pin should be
connected to VCCINT or GNDINT, respectively.
(12) When using the EPF10K100B device, connect this pin to VCCINT.
(13) When using the EPF10K100B device, connect this pin to GNDINT.
(14) The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins.
Tables 87 through 89 show the dedicated pin-outs for FLEX 10KE devices
in 256-pin FineLine BGA, 484-pin FineLine BGA, and 672-pin FineLine
BGA packages.
Table 87. FLEX 10KE FineLine BGA Device Pin-Outs (Part 1 of 4)
Notes (1), (2)
Pin Name
256-Pin
FineLine BGA
EPF10K30E
256-Pin
FineLine BGA
EPF10K50E
EPF10K50S
EPF10K100E
EPF10K100B
484-Pin
FineLine BGA
EPF10K30E
MSEL0
(3)
P1
U4
MSEL1
(3)
R1
V4
nSTATUS
(3)
T16
W19
nCONFIG
(3)
N4
T7
DCLK
(3)
B2
E5
CONF_DONE
(3)
C15
F18
INIT_DONE
(4)
G16
K19
nCE
(3)
B1
E4
nCEO
(3)
B16
E19
nWS
(5)
B14
E17
nRS
(5)
C14
F17
相关PDF资料
PDF描述
EPF10K30EFC256-3 Field Programmable Gate Array (FPGA)
EPF10K30EFC256-3DX ASIC
EPF10K30EFC484-1 Field Programmable Gate Array (FPGA)
EPF10K30EFC484-1DX ASIC
EPF10K30EFC484-1X Field Programmable Gate Array (FPGA)
相关代理商/技术参数
参数描述
EPF10K30EFC256-3 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 176 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K30EFC256-3DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
EPF10K30EFC256-3N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 176 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K30EFC484-1 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 216 LABs 220 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K30EFC484-1DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
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