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参数资料
型号： EPF10K50VRI240-3N
厂商： Altera
文件页数： 46/128页
文件大小： 0K
描述： IC FLEX 10KV FPGA 50K 240-RQFP
产品培训模块： Three Reasons to Use FPGA's in Industrial Designs
产品变化通告： Package Change 30/Jun/2010
标准包装： 24
系列： FLEX-10K®
LAB/CLB数： 360
逻辑元件/单元数： 2880
RAM 位总计： 20480
输入/输出数： 189
门数： 116000
电源电压： 3 V ~ 3.6 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 240-BFQFP 裸露焊盘
供应商设备封装： 240-RQFP（32x32）
24
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If DATA3 is tied to VCC, asserting
LABCTRL1
asynchronously loads a one into the register. Alternatively, the
Altera software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC,
therefore, asserting LABCTRL1 asynchronously loads a one into the
register, effectively presetting the register. Asserting LABCTRL2 clears the
register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling
the register preset and clear.
相关PDF资料
PDF描述
AMM25DRMD-S288 CONN EDGECARD 50POS .156 EXTEND
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相关代理商/技术参数
参数描述
EPF10K50VRI240-4 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K50VRI240-4N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K70 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:EMBEDDED PROGRAMMABLE LOGIC FAMILY
EPF10K70RC240-2 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K70RC240-2N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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