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| 型号： | EPM240T100I5N |
| 厂商： | Altera |
| 文件页数： | 1/6页 |
| 文件大小： | 0K |
| 描述： | IC MAX II CPLD 240 LE 100-TQFP |
| 产品变化通告： | Bond Wire Change 4/Sept/2008 |
| 标准包装： | 270 |
| 系列： | MAX® II |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.7ns |
| 电压电源 - 内部： | 2.5V，3.3V |
| 逻辑元件/逻辑块数目： | 240 |
| 宏单元数： | 192 |
| 输入/输出数： | 80 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 603 (CN2011-ZH PDF) |
| 其它名称： | 544-2276 |
1. Introduction
Introduction
The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m,
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices
offer high I/O counts, fast performance, and reliable fitting versus other CPLD
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed to reduce
cost and power while providing programmable solutions for applications such as bus
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device
configuration control.
Features
The MAX II CPLD has the following features:
■
Low-cost, low-power CPLD
■
Instant-on, non-volatile architecture
■
Standby current as low as 25 A
■
Provides fast propagation delay and clock-to-output times
■
Provides four global clocks with two clocks available per logic array block (LAB)
■
UFM block up to 8 Kbits for non-volatile storage
■
MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V
■
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
■
Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
■
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
■
I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
■
Supports hot-socketing
■
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
■
ISP circuitry compliant with IEEE Std. 1532
MII51001-1.9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM240T100I5NRR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100I5RR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240Z | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:MAX II Device Family Data |
| EPM240Z100C5N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m, |
| EPM240ZF100A | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:MAX II Device Family |
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