参数资料
型号: EPM3032ALI44-10N
厂商: Altera
文件页数: 43/46页
文件大小: 0K
描述: IC MAX 3000A CPLD 32 44-PLCC
标准包装: 390
系列: MAX® 3000A
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 2
宏单元数: 32
门数: 600
输入/输出数: 34
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.58x16.58)
包装: 管件
6
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Macrocells
MAX 3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three
functional blocks: logic array, product–term select matrix, and
programmable register. Figure 2 shows a MAX 3000A macrocell.
Figure 2. MAX 3000A Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product–term select matrix
allocates these product terms for use as either primary logic inputs (to the
OR
and XOR gates) to implement combinatorial functions, or as secondary
inputs to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product–term
allocation according to the logic requirements of the design.
Product-
Term
Select
Matrix
36 Signals
from PIA
16 Expander
Product Terms
LAB Local Array
Parallel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear
Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
Q
ENA
Register
Bypass
To I/O
Control
Block
To PIA
Programmable
Register
VCC
D/T
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