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| 型号： | EPM3128ATC144-5 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 34/53页 |
| 文件大小： | 839K |
| 代理商： | EPM3128ATC144-5 |
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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
MAX 3000A devices contain 32 to 256 macrocells, combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmable-AND/fixed-OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and high-speed parallel expander
product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 3000A devices to be used
in mixed-voltage systems.
MAX 3000A devices are supported by the MAX+PLUS II development
system, an integrated package that offers schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The
MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL,
Verilog HDL, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and UNIX-
workstation-based EDA tools. The MAX+PLUS II software runs on
Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series
700/800, and IBM RISC System/6000 workstations.
f For more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet.
Functional
Description
The MAX 3000A architecture includes the following elements:
s
Logic array blocks (LABs)
s
Macrocells
s
Expander product terms (shareable and parallel)
s
Programmable interconnect array (PIA)
s
I/O control blocks
The MAX 3000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 3000A devices.
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| EPM3128ATC144-5N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3128ATC144-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3128ATC144-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3128ATI100-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3128ATI10010N | 制造商:Altera Corporation 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100-Pin TQFP 制造商:Altera Corporation 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz 3.3V 100-Pin TQFP 制造商:Altera 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100-Pin TQFP 制造商:Altera 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz 3.3V 100-Pin TQFP |
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