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| 型号： | EPM3256AQC208-10N |
| 厂商： | Altera |
| 文件页数： | 34/46页 |
| 文件大小： | 0K |
| 描述： | IC MAX 3000A CPLD 256 208-PQFP |
| 标准包装： | 72 |
| 系列： | MAX® 3000A |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 10.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 16 |
| 宏单元数： | 256 |
| 门数： | 5000 |
| 输入/输出数： | 158 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
| 包装： | 托盘 |
| 产品目录页面： | 603 (CN2011-ZH PDF) |
| 其它名称： | 544-1988 EPM3256AQC208-10N-ND |
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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
MAX 3000A devices contain 32 to 512 macrocells, combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmable–AND/fixed–OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and high–speed parallel
expander product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speed–critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non–speed–critical signals are switching. The output drivers of all
MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used
in mixed–voltage systems.
MAX 3000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry–standard PC– and UNIX–workstation–based EDA tools. The
software runs on Windows–based PCs, as well as Sun SPARCstation, and
HP 9000 Series 700/800 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
The MAX 3000A architecture includes the following elements:
■
Logic array blocks (LABs)
■
Macrocells
■
Expander product terms (shareable and parallel)
■
Programmable interconnect array (PIA)
■
I/O control blocks
The MAX 3000A architecture includes four dedicated inputs that can be
used as general–purpose inputs or as high–speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 3000A devices.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM3256AQC208-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AQC208-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AQI208-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AQI208-10N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256ATC100-5N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Higha??performance, lowa??cost CMOS EEPROMa??based programmable |
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