- 您现在的位置：买卖IC网 > PDF目录19517 > EPM7128AETI144-7N (Altera)IC MAX 7000 CPLD 128 144-TQFP PDF资料下载
参数资料
| 型号： | EPM7128AETI144-7N |
| 厂商： | Altera |
| 文件页数： | 64/64页 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 128 144-TQFP |
| 产品变化通告： | Bond Wire Change 4/Sept/2008 |
| 标准包装： | 180 |
| 系列： | MAX® 7000A |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 8 |
| 宏单元数： | 128 |
| 门数： | 2500 |
| 输入/输出数： | 100 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
| 包装： | 托盘 |
| 其它名称： | 544-2587 EPM7128AETI144-7N-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页当前第64页
Altera Corporation
9
MAX 7000A Programmable Logic Device Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera software then selects the most efficient flipflop operation for each
registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
Global clock signal. This mode achieves the fastest clock-to-output
performance.
■
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
■
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement of
either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry. Upon power-up, each register in EPM7128A and
EPM7256A devices are set to a low state.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
相关PDF资料 |
PDF描述 |
|---|---|
| TPSR105M020R6000 | CAP TANT 1UF 20V 20% 0805 |
| S3B-13-F | DIODE GPP 3A 100V SMC |
| R24P212S/X2/P/R6.4 | CONV DC/DC 2W 24VIN 12VOUT |
| VI-B0K-CY-F1 | CONVERTER MOD DC/DC 40V 50W |
| RCA10DTBD | CONN EDGECARD 20POS R/A .125 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7128AEUC169-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AEUC169-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AEUC169-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AFC100-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7128AFC100-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。