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| 型号： | EPM7160E |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可编程逻辑器件系列 |
| 文件页数： | 11/62页 |
| 文件大小： | 1173K |
| 代理商： | EPM7160E |
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Altera Corporation
11
MAX 7000 Programmable Logic Device Family Data Sheet
Each programmable register can be clocked in three different modes:
■
By a global clock signal. This mode achieves the fastest clock-to-
output performance.
By a global clock signal and enabled by an active-high clock
enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.
By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macrocells or I/ O pins.
■
■
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedicated clock pin,
GCLK1
, as shown in
Figure1
.
In MAX 7000E and MAX 7000S devices, two global clock signals are
available. As shown in
Figure2
, these global clock signals can be the
true or the complement of either of the global clock pins,
GCLK1
or
GCLK2
.
Each register also supports asynchronous preset and clear functions.
As shown in
Figures 3
and
4
, the product-term select matrix allocates
product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high,
active-low control can be obtained by inverting the signal within the
logic array. In addition, each register clear function can be
individually driven by the active-low dedicated global clear pin
(
GCLRn
). Upon power-up, each register in the device will be set to a
low state.
All MAX 7000E and MAX 7000S I/ O pins have a fast input path to a
macrocell register. This dedicated path allows a signal to bypass the
PIA and combinatorial logic and be driven to an input D flipflop with
an extremely fast (2.5 ns) input setup time.
Expander Product Terms
Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7160ELC84-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 160 Macro 64 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7160ELC8412 | 制造商:Altera Corporation 功能描述: |
| EPM7160ELC84-12 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 160 Macro 64 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7160ELC84-15 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 160 Macro 64 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7160ELC84-20 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 160 Macro 64 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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