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| 型号： | EPM7192EQI160-7 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 56/60页 |
| 文件大小： | 1030K |
| 代理商： | EPM7192EQI160-7 |
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Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX-workstation-based EDA tools. The
software runs on Windows-based PCs, as well as Sun SPARCstation, and
HP 9000 Series 700/800 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
The MAX 7000A architecture includes the following elements:
I
Logic array blocks (LABs)
I
Macrocells
I
Expander product terms (shareable and parallel)
I
Programmable interconnect array
I
I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7192QC160-12 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 192-CELL, 12NS PROP DELAY, 160 Pin, Plastic, QFP |
| epm7192qc160-2 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 192-CELL, 20NS PROP DELAY, 160 Pin, Plastic, QFP |
| EPM7192QC160-20 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 192-CELL, 20NS PROP DELAY, 160 Pin, Plastic, QFP |
| EPM7192S | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPM7192SQC160-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 192 Macro 124 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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