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参数资料
型号： EPM7192S
厂商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可编程逻辑器件系列
文件页数： 18/62页
文件大小： 1173K
代理商： EPM7192S
18
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Open-Drain Output Option (MAX 7000S Devices Only)
MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/ O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-
OR
plane.
By using an external 5.0-V pull-up resistor, output pins on MAX 7000S
devices can be set to meet 5.0-V CMOS input voltages. When V
CCIO
is
3.3V, setting the open drain option will turn off the output pull-up
transistor, allowing the external pull-up resistor to pull the output high
enough to meet 5.0-V CMOS input voltages. When V
CCIO
is 5.0V, setting
the output drain option is not necessary because the pull-up transistor will
already turn off when the pin exceeds approximately 3.8 V, allowing the
external pull-up resistor to pull the output high enough to meet 5.0-V
CMOS input voltages.
Slew-Rate Control
The output buffer for each MAX 7000E and MAX 7000S I/ O pin has an
adjustable output slew rate that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay of 4 to 5 ns. In MAX 7000E devices, when the
Turbo Bit is turned off, the slew rate is set for low noise performance. For
MAX 7000S devices, each I/ O pin has an individual EEPROM bit that
controls the slew rate, allowing designers to specify the slew rate on a
pin-by-pin basis.
Programming
with External
Hardware
MAX 7000 devices can be programmed on Windows-based PCs with the
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs a continuity
check to ensure adequate electrical contact between the adapter and the
device.
f
Altera Programming Hardware Data Sheet
.
The Altera development system can use text- or waveform-format test
vectors created with the Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional behavior of a
MAX 7000 device with the results of simulation. Moreover, Data I/ O, BP
Microsystems, and other programming hardware manufacturers also
provide programming support for Altera devices.
f
For more information, see the
Programming Hardware Manufacturers
.
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相关代理商/技术参数
参数描述
EPM7192SQC160-10 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 192 Macro 124 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7192SQC160-10F 功能描述:IC MAX 7000 CPLD 192 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:MAX® 7000 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘
EPM7192SQC160-10N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 192 Macro 124 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7192SQC160-15 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 192 Macro 124 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7192SQC160-15F 功能描述:IC MAX 7000 CPLD 192 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:MAX® 7000 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘
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