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参数资料
型号： EPM7256AETC100-5
厂商： Altera
文件页数： 18/64页
文件大小： 0K
描述： IC MAX 7000 CPLD 256 100-TQFP
标准包装： 270
系列： MAX® 7000A
可编程类型： 系统内可编程
最大延迟时间 tpd(1)： 5.5ns
电压电源 - 内部： 3 V ~ 3.6 V
逻辑元件/逻辑块数目： 16
宏单元数： 256
门数： 5000
输入/输出数： 84
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 100-TQFP
供应商设备封装： 100-TQFP（14x14）
包装： 托盘
其它名称： 544-2058
EPM7256AETC100-5-ND
Altera Corporation
25
MAX 7000A Programmable Logic Device Data Sheet
Open-Drain Output Option
MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. This
output can also provide an additional wired-OR plane.
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high
VIH. When the open-drain pin is active, it will drive low. When the pin is
inactive, the resistor will pull up the trace to 5.0 V to meet CMOS VOH
requirements. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor.
Programmable Ground Pins
Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the rising
and falling edges of the output signal.
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相关代理商/技术参数
参数描述
EPM7256AETC100-5N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256AETC100-7 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256AETC100-7N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256AETC144-10 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256AETC14410N 制造商:Altera Corporation 功能描述:CPLD MAX 7000 256 MACROCELLS TQFP144 制造商:Altera Corporation 功能描述:CPLD, MAX 7000, 256 MACROCELLS, TQFP144
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