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参数资料
| 型号： | EPM7256AETI100-6 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 6 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 7/51页 |
| 文件大小： | 1559K |
| 代理商： | EPM7256AETI100-6 |
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Altera Corporation
609
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
In-System
Programma-
bility (ISP)
MAX 7000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. ISP offers quick,
efficient iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 k
.
MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices only.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick-and-place equipment
before they are programmed. MAX 7000A devices can be programmed by
downloading the information via in-circuit testers, embedded processors,
the Altera BitBlaster serial download cable, and the ByteBlasterMV
parallel port download cable. Programming the devices after they are
placed on the board eliminates lead damage on high-pin-count packages
(e.g., QFP packages) due to device handling. MAX 7000A devices can be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support an adaptive algorithm, Altera offers devices tested with a
constant algorithm. Devices tested to the constant algorithm contain an
“F” suffix in the ordering code and are marked with an “F” on the bottom
right-hand corner of the device.
The Jam programming and test language can be used to program
MAX 7000A devices with in-circuit testers, PCs, or embedded processors.
f For more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor).
相关PDF资料 |
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| EPM7128AETC144-4 | EE PLD, 4.5 ns, PQFP144 |
| EPM7128AETC144-6 | EE PLD, 6 ns, PQFP144 |
| EPM7128AETI144-6 | EE PLD, 6 ns, PQFP144 |
| EPM7256AETC144-6 | EE PLD, 6 ns, PQFP144 |
| EPM7256AETI144-6 | EE PLD, 6 ns, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7256AETI100-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7256AETI100-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7256AETI144-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7256AETI144-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7256AFC256-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
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