参数资料
型号: EPM7256SRC208-10
厂商: Altera
文件页数: 15/66页
文件大小: 0K
描述: IC MAX 7000 CPLD 256 208-RQFP
产品变化通告: Package Change 30/Jun/2010
标准包装: 24
系列: MAX® 7000
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 4.75 V ~ 5.25 V
逻辑元件/逻辑块数目: 16
宏单元数: 256
门数: 5000
输入/输出数: 164
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-BFQFP 裸露焊盘
供应商设备封装: 208-RQFP(28x28)
包装: 托盘
其它名称: 544-2067
EPM7256SRC208-10-ND
22
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.
1149.1-1990. Table 9 describes the JTAG instructions supported by the
MAX 7000 family. The pin-out tables (see the Altera web site
(http://www.altera.com) or the Altera Digital Library for pin-out
information) show the location of the JTAG control pins for each device.
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.
Table 9. MAX 7000 JTAG Instructions
JTAG Instruction
Devices
Description
SAMPLE/PRELOAD
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern output at the device pins.
EXTEST
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
BYPASS
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Places the 1-bit bypass register between the TDI and TDO pins, which
allows the BST data to pass synchronously through a selected device
to adjacent devices during normal device operation.
IDCODE
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
ISP Instructions
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
These instructions are used when programming MAX 7000S devices
via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster
download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),
or Serial Vector Format file (.svf) via an embedded processor or test
equipment.
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相关代理商/技术参数
参数描述
EPM7256SRC208-10N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256SRC208-15 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256SRC208-15N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256SRC208-7 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7256SRC208-7N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100