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| 型号： | EPM7512AEQI208-10N |
| 厂商： | Altera |
| 文件页数： | 17/64页 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 512 208-PQFP |
| 标准包装： | 72 |
| 系列： | MAX® 7000A |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 10.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 32 |
| 宏单元数： | 512 |
| 门数： | 10000 |
| 输入/输出数： | 176 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
| 包装： | 托盘 |
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24
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Programmable
Speed/Power
Control
MAX 7000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000A
device for either high-speed (i.e., with the Turbo BitTM option turned on)
or low-power operation (i.e., with the Turbo Bit option turned off). As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC,
tEN, tSEXP, tACL, and tCPPW parameters.
Output
Configuration
MAX 7000A device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
The MAX 7000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 7000A devices to connect to systems with
differing supply voltages. MAX 7000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
VCC
pins for internal operation and input buffers (VCCINT), and another
set for I/O output drivers (VCCIO).
The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 2.5-V power supply, the output levels are compatible with
2.5-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with VCCIO levels lower than 3.0 V
incur a slightly greater timing delay of tOD2 instead of tOD1. Inputs can
always be driven by 2.5-V, 3.3-V, or 5.0-V signals.
Table 12 describes the MAX 7000A MultiVolt I/O support.
Table 12. MAX 7000A MultiVolt I/O Support
VCCIO Voltage
Input Signal (V)
Output Signal (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
vvvv
3.3
vvv
vv
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相关代理商/技术参数 |
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| EPM7512AETC100-10 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX |
| EPM7512AETC14410 | 制造商:Altera Corporation 功能描述: |
| EPM7512AETC144-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512AETC144-10N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512AETC144-12 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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