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参数资料
| 型号： | EPM7512AETC144-12 |
| 文件页数： | 12/60页 |
| 文件大小： | 1041K |
| 代理商： | EPM7512AETC144-12 |
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Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
...and More
Features
I
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
I
MultiVoltTM I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
I
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
I
Supports hot-socketing in MAX 7000AE devices
I
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
I
PCI-compatible
I
Bus-friendly architecture, including programmable slew-rate control
I
Open-drain output option
I
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
I
Programmable power-up states for macrocell registers in
MAX 7000AE devices
I
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
I
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
I
Programmable security bit for protection of proprietary designs
I
6 to 10 pin- or logic-driven output enable signals
I
Two global clock signals with optional inversion
I
Enhanced interconnect resources for improved routability
I
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
I
Programmable output slew-rate control
I
Programmable ground pins
I
Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
I
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
I
Programming support with Altera’s Master Programming Unit
(MPU), MasterBlasterTM serial/universal serial bus (USB)
communications cable, ByteBlasterMVTM parallel port download
cable, and BitBlasterTM serial download cable, as well as
programming hardware from third-party manufacturers and any
JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector
Format File- (.svf) capable in-circuit tester
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7512AETC144-12N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512AETC1447 | 制造商:Altera Corporation 功能描述: |
| EPM7512AETC144-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512AETC144-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512AETI100-7 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX |
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