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| 型号： | EPM7512BBC256-7 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 5.5 ns, PBGA256 |
| 封装： | BGA-256 |
| 文件页数： | 11/66页 |
| 文件大小： | 962K |
| 代理商： | EPM7512BBC256-7 |
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Altera Corporation
19
MAX 7000B Programmable Logic Device Data Sheet
Programming
with External
Hardware
MAX 7000B devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000B devices include the JTAG boundary-scan test circuitry
defined by IEEE Std. 1149.1. Table 6 describes the JTAG instructions
supported by MAX 7000B devices. The pin-out tables starting on page 59
of this data sheet show the location of the JTAG control pins for each
device. If the JTAG interface is not required, the JTAG pins are available
as user I/O pins.
Table 6. MAX 7000B JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the
boundary-scan test data to pass synchronously through a selected device to adjacent
devices during normal operation.
CLAMP
Allows the values in the boundary-scan register to determine pin states while placing the
1-bit bypass register between the TDI and TDO pins.
IDCODE
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO.
ISP Instructions
These instructions are used when programming MAX 7000B devices via the JTAG ports
with the MasterBlaster or ByteBlasterMV download cable, or using a Jam File (.jam),
Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded
processor or test equipment.
相关PDF资料 |
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|---|---|
| EPM7512BFC256-10 | EE PLD, 5.5 ns, PBGA256 |
| EPM7512BFC256-7 | EE PLD, 5.5 ns, PBGA256 |
| EPM7512BFI256-10 | EE PLD, 5.5 ns, PBGA256 |
| EPM7512BFI256-7 | EE PLD, 5.5 ns, PBGA256 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7512BBI256-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7512BFC256-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512BFC256-5 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512BFC256-5N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512BFC256-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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