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参数资料
| 型号： | EPM7512BFI256-7 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 5.5 ns, PBGA256 |
| 封装： | FBGA-256 |
| 文件页数： | 8/66页 |
| 文件大小： | 962K |
| 代理商： | EPM7512BFI256-7 |
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Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 7000B device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
A pulse time to erase, program, or read the EEPROM cells.
■
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
相关PDF资料 |
PDF描述 |
|---|---|
| EPM7512BQC208-10 | EE PLD, 5.5 ns, PQFP208 |
| EPM7512BQC208-7 | EE PLD, 5.5 ns, PQFP208 |
| EPM7512BTC144-10 | EE PLD, 5.5 ns, PQFP144 |
| EPM7512BTC144-7 | EE PLD, 5.5 ns, PQFP144 |
| EPM7512BBC256-5 | EE PLD, 5.5 ns, PBGA256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7512BQC208-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512BQC208-5 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512BQC208-6 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述: |
| EPM7512BQC208-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7512BTC144-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 512 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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