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| 型号： | EPM9560RC240-15 |
| 厂商： | Altera |
| 文件页数： | 13/46页 |
| 文件大小： | 0K |
| 描述： | IC MAX 9000 CPLD 560 240-RQFP |
| 产品变化通告： | Package Change 30/Jun/2010 |
| 标准包装： | 24 |
| 系列： | Max® 9000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 35 |
| 宏单元数： | 560 |
| 门数： | 12000 |
| 输入/输出数： | 191 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BFQFP 裸露焊盘 |
| 供应商设备封装： | 240-RQFP（32x32） |
| 包装： | 托盘 |
| 其它名称： | 544-2366 |
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20
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 9000 device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
A pulse time to erase, program, or read the EEPROM cells.
■
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM9560RC240-15YY | 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz CMOS Technology 5V 240-Pin RQFP 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz 5V 240-Pin RQFP |
| EPM9560RC240-20 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM9560RC304-15 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM9560RI208-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述: |
| EPM9560RI208-20 | 制造商:Altera Corporation 功能描述:IC MAX |
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