ePVP6300
VFD Controller
6 of 63
11.04.2004
(V1.92)
This specification is subject to change without further notice.
6 Pin Descriptions
Pin No.
Pin Name
I/O #
Description
Note
61,62
NC
2
13,14
VDD
-
2 Logic power supply
57
STB/GPIOC4
I/O 1
1. Serial Interface Strobe input pin. While the STB goes low, it
will cause interrupt event. The data input after the STB has
fallen is processed as a command. When this pin is “HIGH,”
CLK is ignored.
2. Programmable Internal pull high
3. GPIOC4 function
Schmitt
Pull-up
58
CLK/GPIOC5
I/O 1
1. Clock input pin. This pin reads serial data at the rising edge
and outputs data at the falling edge.
2. Programmable Internal pull high
3. GPIOC5 function
Schmitt
Pull-up
59
DOUT/GPIOC6
I/O 1
1. Data output pin (N-channel, Open-Drain)
2. This pin outputs serial data at the falling edge of the shift clock
(starting from lower bit).
3. Programmable internal pull high
4. GPIOC6 function
Schmitt
Pull-up
60
DIN/GPIOC7
I/O 1
1. Data input pin. This pin inputs serial data at the rising edge of
the shift clock (starting from lower bit.)
2. Programmable Internal pull high
3. GPIOC7 function
Schmitt
Pull-up
53 – 54
GPIOC0 – GPIOC3
I/O 4
General Purpose I/O pins
:
1. Key data input to these pins is latched at the end of display
cycle.
2. These pins constitute 4-bit general-purpose input/output port.
3. Programmable Internal Pull-High
4. Wake-up Function
Schmitt
Pull-up
15-22
(B Cell)
GR1 – GR8
O
8
1. High voltage grid output
2. High breakdown output
~
23-30
(B Cell)
GR9/P9/SG20
–
GR16/ SG13
O
8
1. High voltage grid output
2. High breakdown output
3. High voltage segment output
31-33
(B Cell)
GR17/SG12/KS12
–
GR19 /SG10/KS10
O
3
1. High voltage grid output
2. High breakdown output
3. High voltage segment output
4. Matrix key scan output
34-38
(A Cell)
SG9/KS9
–
SG5/KS5
O
5
1. High breakdown output
2. High voltage segment output
3. Matrix key scan output